The present invention relates to a pulse generator, and more particularly to a pulse generator for generating a basic pulse signal activating read/write internal operations of a synchronous semiconductor memory device wherein an internal access is made by utilizing two or more clock cycles as a cycle unit.
A conventional pulse signal generator has a circuit configuration as illustrated in FIG. 1. This conventional pulse signal generator has the following disadvantage. A pulse signal generation timing is largely delayed from input of the clock signal CLK. The conventional circuit configuration is such that a short pulse signal "B" is once generated in accordance with a logic signal "A" based upon the clock signal and the action commence signal "AC". This means it necessary to form three logic gate stages. This short pulse generation circuit is necessary. If no short pulse generation circuit is provided, the following problems will appear. If the high level time period of the clock signal CLK is short, a reset appear due to the low level of the clock signal CLK on the delay circuit which defines the pulse width of the next stage, whereby the pulse signal may be discontinued.
The conventional pulse signal generator of FIG. 1 has a further disadvantage as follows. A pulse width is variable depending upon variations on characteristics of the transistors due to variations in environmental conditions such as temperature and power voltage level as well as due to variations in manufacturing conditions. The conventional circuit configuration is such that the pulse width is defined by a total time of first and second delay times respectively provided by first and second delay circuits 26 and 27. This circuit normally comprises series connections of plural stages of invertors. This delay time is just influenced by variations of the capability of the MOS transistors in the invertors.
In the above circumstances, it had been required to develop a novel pulse generator free from the above problems and generating a basic pulse signal activating read/write internal operations of a synchronous semiconductor memory device wherein an internal access is made by utilizing two or more clock cycles as a cycle unit.